工作单位

中国科学技术大学先进技术研究院/中国科学技术大学微电子学院

学位/职称

博士/副教授

办公室电话

0551-63602675

Email

songch@ustc.edu.cn

教育背景

1996/9～2000/7 西安交通大学   本科 计算机科学与技术

2000/9～2005/7 清华大学   硕士、博士 计算机科学与技术

研究方向

专用芯片体系架构、FPGA应用、电子设计自动化。研究方向包括存算融合高能效芯片架构；基于FPGA的人工智能加速器设计；大规模集成电路优化技术等。

任职经历

2019/4～至今     中国科学技术大学 副教授

2012/9～2019/3 中国科学技术大学   轨道制副教授

2009/4～2012/8    日本早稻田大学 助理教授

2008/4～2009/3    日本早稻田大学 访问讲师

2005/8～2008/3    日本早稻田大学 访问副研究员

获得荣誉、奖项

2018年中国科学技术大学校级“优秀博士学位论文”指导老师

2017年第一届全国大学生集成电路创新创业大赛优秀指导老师（指导学生获全国总决赛二等奖）

主持、参与项目

国家自然科学基金面上项目（青年）：应用射频互连的低功耗专用片上网络体系结构综合研究   2015/1~2017/12（主持，结题）

国家自然科学基金面上项目：动态可重构专用片上网络架构综合关键技术研究 2017/1~2017/12 （主持，结题）

国家自然科学基金委面上项目 脑网络启发的大规模神经形态系统片上互连结构综合2019.01-2022.12 (主持)

国家自然科学基金委重点项目子课题 基于忆阻器的大规模神经网络的类脑计算架构研究2018.01-2022.12 (主持)

中国科学院先导B课题 面向智能内存的软件系统2020.1~2024.12（主持）

科技部重点研发计划项目 基于DRAM的存算一体架构   2020.1~2023.12(参与)

论文、著作

[1]  Qi Xu, Hao Geng,   Tianming Ni, Song Chen, Bei Yu, Yi Kang, and Xiaoqing Wen,   "Fortune: A New Fault-Tolerance TSV Configuration in Router-based   Redundancy Structure", IEEE Transactions on Computer-Aided   Design of Integrated Circuits and Systems , 2021 (accepted) (Full Text in IEEE   Xplore).

[2]  Qi Xu, Hao   Geng, Song Chen, Bo Yuan, Cheng Zhuo, Yi Kang, Xiaoqing Wen,   "GoodFloorplan: Graph Convolutional Network and Reinforcement Learning   Based Floorplanning", IEEE Transactions on Computer-Aided Design   of Integrated Circuits and Systems , 2021 (accepted) (Full Text in IEEE   Xplore).

[3]  Qi Xu, Junpeng   Wang, Bo Yuan, Qi Sun, Song Chen, Bei Yu, Yi Kang and Feng Wu,   "Reliability-Driven Memristive Crossbar Design in Neuromorphic Computing   Systems", IEEE Transactions on Automation Science and   Engineering (TASE) , 2021 (accepted) (Full Text in IEEE Xplore)

[4]  Mengke Ge, Bingxiao   Ni, Song Chen, and Yi Kang, "Generating   Brain-Network-Inspired Toplogies for Large-Scale NoCs on Monolithic 3D   ICs", IEEE Transactions on Circuits and Systems II: Express   Briefs , 2021 (accepted) (Full Text in IEEE Xplore)

[5]  Mengke Ge, Bingxiao   Ni, Qi Xu, Jinglei Huang, Song Chen, Yi Kang, Feng Wu,   "Synthesizing Brain-Network-Inspired Interconnections for Large-Scale   Network-on-Chips", ACM Transactions on Design Automation of   Electronic Systems , 27(1), 9:1-9:30 2021 (Full Text in ACM DL)

[6]  Qi Xu, Wenhao   Sun, Song Chen, Yi Kang and Xiaoqin Wen. Cellular Structure Based   Fault-Tolerance TSV Configuration in 3D-IC. IEEE Transactions on   Computer-Aided Design of Integrated Circuits and Systems, 2021.   (online, Full Text in IEEE Xplore ) doi:   10.1109/TCAD.2021.3084920

[7]  Zhimin Lu, Jue   Wang, Zhiwei Li, Song Chen and Feng Wu. A Resource-Efficient   Pipelined Architecture for Real-Time Semi-Global Stereo Matching. IEEE   Transactions on Circuits and Systems for Video Technology, 2021.   (online, Full Text in IEEE Xplore ) doi:   10.1109/TCSVT.2021.3061704.

[8]  Song Chen , Mengke Ge,   Zhigang Li, Jinglei Huang, Qi Xu, and Feng Wu. Generalized Fault-Tolerance   Topology Generation for Application Specific Network-on-Chips. IEEE   Transactions on Computer-Aided Design of Integrated Circuits and Systems,   vol. 39, no. 6, pp. 1191-1204, June 2020.( Full Text in IEEE Xplore )

[9]  Song Chen , Jinglei   Huang, Xiaodong Xu, Bo Ding, Qi Xu, “Integrated Optimization of   Partitioning, Scheduling, and Floorplanning for Partially Dynamically   Reconfigurable Systems”, IEEE Transactions on   Computer-Aided Design of Integrated Circuits and Systems , October,   Vol.39, No.1, pp.199-212, January 2020.(Full   Text in IEEE Xplore)

[10]    Qi Xu, Song Chen , Hao Geng, Bo Yuan,   Bei Yu, Feng Wu, Zhengfeng Huang, “Fault Tolerance in Memristive   Crossbar-Based Neuromorphic Computing Systems”, Integration-the   VLSI Journal, vol. 70, Jan., pp. 70–79, 2020. (online)

[11]    Qi Xu, Hao Geng, Song Chen , Bei Yu,   Feng Wu, “Memristive   Crossbar Mapping for Neuromorphic Computing Systems on 3D IC”, ACM Transactions on Design Automation of Electronic   Systems (TODAES), vol. 25, no. 1, pp. 8:1–8:19,   2019.

[12]    Song Chen, Qi Xu, Bei Yu, “Adaptive 3D-IC TSV Fault Tolerance   Structure Generation”, IEEE Transactions on   Computer-Aided Design of Integrated Circuits and Systems , 38(5),   pp.949-960,2019. (Full Text in IEEE Xplore)

[13]    Jinglei Huang, Xiaodong Xu, Nan Wang, Song Chen ,   "Reconfigurable Topology Synthesis for Application-Specific NoC on   Partially Dynamically Reconfigurable Systems", Integration-the   VLSI Journal, Volume 65, March 2019, Pages 331-343.

[14]    Yan Li, Zhiwei Li, Chen Yang, Wei Zhong, and Song   Chen, “High   throughput Hardware architecture for accurate semi-global matching”, Integration-the VLSI Journal, Volume 65, March 2019,   Pages 417-427.

[15]    Nan Wang, Song Chen, Zhiyuan Ma, Xiaofeng   Ling, Yu Zhu, “Integrating   Operation Scheduling and binding for functional unit power-gating in   high-level synthesis”, Integration-the VLSI   Journal, Volume 65, March 2019, Pages 308-321.

[16]    Nan Wang, Wei Zhong, Song Chen ,   Zhiyuan Ma, Xiaofeng Ling, and Yu Zhu, “Power-gating-aware scheduling with   effective hardware resources optimization”, Integration-the   VLSI Journal, Vol.61, pp.167-177, 2018.

[17]    Jinglei Huang, Wei Zhong, Zhigang Li, Song Chen ,   "Lagrangian relaxation-based routing path allocation for   application-specific network-on-chips", Integration-the VLSI   Journal, Vol. 61, pp.20-28, 2018.

[18]    Qi Xu, Song Chen, "Fast thermal analysis for   fixed-outline 3D floorplanning", Integration-the VLSI Journal,   September 2017 Vol. 58 No.9, pp.157-167.

[19]    Qi Xu, Song Chen , Xiaodong Xu, Bei   Yu, "Clustered Fault Tolerance TSV Planning for 3D Integrated   Circuits", IEEE Transactions on Computer-Aided Design of   Integrated Circuits and Systems. Vol. 36, No.8, pp. 1287-1300, Aug.   2017.(Full Text in IEEE Xplore)

[20]    Gan Feng, Lan Yao, Song Chen,   "AutoNFT: Architecture Synthesis for Hardware DFT of Length of   Coprime-Number Products", Integration-the VLSI Journal, vol.   58, No.6, pp.339-347, June 2017.

[21]    Nan Wang, Wei Zhong, Cong Hao, Song Chen,   Takeshi Yoshimura, Yu Zhu, "Leakage Power-Aware Scheduling with   Dual-Threshold Voltage Design", IEEE Transactions on Very Large   Scale Integration Systems (VLSI) vol.24, No.10, pp. 3067-3079,2016.   (Full Text in IEEE Xplore)

[22]    Jinglei Huang, Song Chen, Wei Zhong,   Wenchao Zhang, Shengxi Diao, Fujiang Lin, "Floorplanning and Topology   Synthesis for Application Specific Network-on-Chips with   RF-Interconnect", ACM Transactions on Design Automation of   Electronic Systems 21(3):40,23 pages, 2016. (online)

[23]    Qi Xu，Song Chen, Bin Li, “Combining the ant system algorithm and simulated annealing for   3D/2D fixed-outline floorplanning”, Applied   Soft Computing, 40:150-160, 2016/03.

[24]    Nan Wang, Song Chen, Wei Zhong, Nan Liu,   Takeshi Yoshimura, “Mobility   Overlap-Removal-Based Leakage Power and Register-Aware Scheduling in   High-Level Synthesis”, IEICE Transactions on   Fundamentals of Electronics, Communications and Computer Sciences, Vol   E97-A, No.8, pp.1-11(accepted), No.8, 2014.

[25]    Nan Wang, Song Chen, Cong Hao, Haoran   Zhang, and Takeshi Yoshimura, “Leakage Power Aware Scheduling in   High-Level Synthesis ”, IEICE Transactions on   Fundamentals of Electronics, Communications and Computer Sciences, Vol.   E97-A, No.4, pp.940-951, 2014.

[26]    Wei Zhong, Song Chen, Bo Huang, Takeshi   Yoshimura, and Satoshi Goto, “Floorplanning and Topology Synthesis for   Application-Specific Network-on-Chips”, IEICE   Transactions on on Fundamentals of Electronics, Communications and Computer   Sciences,, Vol. E96-A, No.6, pp. 1174- 1184, 2013.

[27]    Nan Liu, Song Chen, and Takeshi Yoshimura, “ Resource-aware   Multi-layer Floorplanning for Partially Reconfigurable FPGAs ”, IEICE Transactions on Electronics, Vol.E96-C, No.4,   pp 501-510, 2013.

[28]    Haiqi WANG, Sheqin DONG, Tao LIN, Song Chen,   and Satoshi GOTO, “   Novel Voltage Choice and Min-Cut Based Assignment for Dual-VDD System ”, IEICE Transactions on Fundmentals of Electronics,   Communications and Computer Sciences, Vol.E95-A No.12, pp 2208-2219,   2012.

[29]    Nan Liu, Song Chen, and Takeshi Yoshimura, “Floorplanning for High   Utilization of Heterogeneous FPGAs ”, IEICE   Transactions on Fundamentals of Electronics, Communications and Computer   Sciences, Vol.E95-A, No.9, pp 1529-1537, 2012.

[30]    Wei Zhong, Takeshi Yoshimura, Bei Yu, Song Chen,   Sheqin Dong and Satoshi Goto, " Cluster Generation and Network Component   Insertion for Topology Synthesis of Application-Specific   Network-on-Chips", IEICE Transactions on Electronics,   Vol.E95-C, NO.4, pp.535-545, April,2012.

[31]    Song Chen, J. Shen, W. Guo, M.F. Chiang, and T. Yoshimura. “ Redundant Via   Insertion: Removing Design Rule Conflicts and Balancing Via Density”, IEICE Transactions on Fundamentals of Electronics,   Communications and Computer Sciences, Vol.E93-A, No.12, Dec. 2010,   pp.2372-2379.

[32]    Song Chen and T. Yoshimura. Multi-layer floorplanning for   stacked ICs: Configuration number and fixed-outline constraints. Integration,   the VLSI journal, 43(4), pp.378-388, 2010. binary package

[33]    Song Chen, Liangwei Ge, Mei-Fang Chiang, Takeshi Yoshimura, “ Lagrangian Relaxation   Based Inter-Layer Signal Via Assignment for 3-D ICs”, IEICE   Transactions on Fundamentals of Electronics, Communications and Computer   Sciences, Vol.E92-A, No.4, pp.1080-1087, 2009.

[34]    Song Chen and T. Yoshimura, “ Fixed-outline floorplanning: Enumerating   block positions and a new objective function for calculating area costs,” IEEE Transactions On CAD of Integrated Circuits and   Systems, vol.27, no. 5, pp.858-871, 2008. (Full Text in IEEE   Xplore)

[35]    Song Chen, S. Dong, X. Hong, and C. Cheng, “Vlsi block placement   with alignment constraints,” IEEE   Transactions on Circuits and Systems II: Express Briefs , vol. 53,   no. 8, pp. 622-626, 2006. (Full Text in IEEE Xplore)

[36]    L. Ge, Song Chen, K. Wakabayashi, T.   Takenaka, and T. Yoshimura, “ Maxflow scheduling in high-level synthesis,” IEICE Transactions on Fundamentals of Electronics,   Communications and Computer Sciences, vol. E90-A, no. 9, pp.1940-1948,   2007.

[37]    L. Ge, Song Chen, Y. Nakamura, and T.   Yoshimura, “   A synthesis method of general floating-point arithmetic units by aligned   partition,” IPSJ Transactions on System LSI   Design Methodology, vol.1, pp. 67-77, Aug. 2008.

[38]    L. Ge, Song Chen, and T. Yoshimura, “ Exploration of   schedule space by random walk,” IPSJ   Transactions on System LSI Design Methodology, vol. 2, pp.30-42, Feb.   2009.

[39]    S. Dong, X. Hong, Song Chen, and et al, “ Vlsi module placement   with pre-placed modules and with consideration of congestion using solution   space smoothing,” IEICE Transactions on   Fundamentals of Electronics, Communications and Computer Sciences,   vol.E86-A, no.12, pp. 3136-3147, 2003.

[40]    B. Yu, S. Dong, Song Chen, and S. Goto. “ Voltage and   level-shifter assignment driven floorplanning”, IEICE   Transactions on Fundamentals of Electronics, Communications and Computer   Sciences, Vol.E92-A, No.12:2990-2997, 2009.

[41]    Y. Ma, X. Hong, S. Dong, Song Chen, and et   al, “   Buffer planning as an integral part of floorplanning with consideration of   routing congestion,” IEEE Transactions on CAD   of Integrated Circuits and Systems, vol.24, no.4, pp.609-621, 2005. ( Full Text in IEEE   Xplore)

[42]    Song Chen, X. Hong, S. Dong, and et al, “ Fast evaluation of   bounded sliceline grid,” Journal of Computer   Science and Technology (Springer), vol.19, no.6, pp. 973-980, 2004.

[43]    Song Chen, X. HOng, S. Dong, and et al, “ A buffer planning   algorithm for chip-level floorplanning,” Science   in China Series F-Information Sciences (Springer), vol.47, no.6,   pp.763-776, 2004.